7 #include <avr/interrupt.h>
12 static volatile uint8_t rx_buf0[
RX0_SIZE];
13 static volatile uint8_t rx_in0, rx_out0;
15 static volatile uint8_t tx_in0, tx_out0;
16 static uint8_t rxtid0;
18 static uint8_t txtid0;
22 static volatile uint8_t rx_buf1[
RX1_SIZE];
23 static volatile uint8_t rx_in1, rx_out1;
25 static volatile uint8_t tx_in1, tx_out1;
26 static uint8_t rxtid1;
28 static uint8_t txtid1;
32 static volatile uint8_t rx_buf2[
RX2_SIZE];
33 static volatile uint8_t rx_in2, rx_out2;
35 static volatile uint8_t tx_in2, tx_out2;
36 static uint8_t rxtid2;
38 static uint8_t txtid2;
42 static volatile uint8_t rx_buf3[
RX0_SIZE];
43 static volatile uint8_t rx_in3, rx_out3;
45 static volatile uint8_t tx_in3, tx_out3;
46 static uint8_t rxtid3;
48 static uint8_t txtid3;
59 UCSR0C = ( 1<<UCSZ01 )^( 1<<UCSZ00 )^( 1<<USBS0 )^( 0<<UPM01 )^( 0<<UPM00 );
60 UCSR0B = ( 1<<RXEN0 )^( 1<<TXEN0 )^( 1<<RXCIE0 );
70 UCSR1C = ( 1<<UCSZ11 )^( 1<<UCSZ10 )^( 1<<USBS1 )^( 0<<UPM11 )^( 0<<UPM10 );
71 UCSR1B = ( 1<<RXEN1 )^( 1<<TXEN1 )^( 1<<RXCIE1 );
81 UCSR2C = ( 1<<UCSZ21 )^( 1<<UCSZ20 )^( 1<<USBS2 )^( 0<<UPM21 )^( 0<<UPM20 );
82 UCSR2B = ( 1<<RXEN2 )^( 1<<TXEN2 )^( 1<<RXCIE2 );
92 UCSR3C = ( 1<<UCSZ31 )^( 1<<UCSZ30 )^( 1<<USBS3 )^( 0<<UPM31 )^( 0<<UPM30 );
93 UCSR3B = ( 1<<RXEN3 )^( 1<<TXEN3 )^( 1<<RXCIE3 );
117 UCSR0B&=~( 1<<RXCIE0 );
120 rx_buf0[rx_in0] = UDR0;
126 if( tx_in0==tx_out0 ) {
131 UCSR0B&=~( 1<<UDRIE0 );
134 UDR0 = tx_buff0[tx_out0];
153 UCSR1B&=~( 1<<RXCIE1 );
156 rx_buf1[rx_in1] = UDR1;
162 if( tx_in1==tx_out1 ) {
167 UCSR1B&=~( 1<<UDRIE1 );
170 UDR1 = tx_buff1[tx_out1];
189 UCSR2B&=~( 1<<RXCIE2 );
192 rx_buf2[rx_in2] = UDR2;
198 if( tx_in2==tx_out2 ) {
203 UCSR2B&=~( 1<<UDRIE2 );
206 UDR2 = tx_buff2[tx_out2];
225 UCSR3B&=~( 1<<RXCIE3 );
228 rx_buf3[rx_in3] = UDR3;
234 if( tx_in3==tx_out3 ) {
239 UCSR3B&=~( 1<<UDRIE3 );
242 UDR3 = tx_buff3[tx_out3];
249 uint8_t
read(
tUART port,
void * puffer, uint8_t nbytes, uint8_t timeout ) {
250 register uint8_t anz=0;
258 UCSR0B|=( 1<<RXCIE0 );
259 while( anz<nbytes ) {
260 if( rx_in0!=rx_out0 ) {
261 *( uint8_t * )puffer++=rx_buf0[rx_out0];
267 ATOMIC_BLOCK( ATOMIC_RESTORESTATE ) {
287 UCSR1B|=( 1<<RXCIE1 );
288 while( anz<nbytes ) {
289 if( rx_in1!=rx_out1 ) {
290 *( uint8_t * )puffer++=rx_buf1[rx_out1];
296 ATOMIC_BLOCK( ATOMIC_RESTORESTATE ) {
316 UCSR2B|=( 1<<RXCIE2 );
317 while( anz<nbytes ) {
318 if( rx_in2!=rx_out2 ) {
319 *( uint8_t * )puffer++=rx_buf2[rx_out2];
325 ATOMIC_BLOCK( ATOMIC_RESTORESTATE ) {
345 UCSR3B|=( 1<<RXCIE3 );
346 while( anz<nbytes ) {
347 if( rx_in3!=rx_out3 ) {
348 *( uint8_t * )puffer++=rx_buf3[rx_out3];
354 ATOMIC_BLOCK( ATOMIC_RESTORESTATE ) {
379 register uint8_t i=tx_in0;
381 if( i!=tx_out0 )
break;
382 ATOMIC_BLOCK( ATOMIC_RESTORESTATE ) {
383 UCSR0B|=( 1<<UDRIE0 );
389 tx_buff0[tx_in0] = *( uint8_t * )puffer++;
391 UCSR0B|=( 1<<UDRIE0 );
400 register uint8_t i=tx_in1;
402 if( i!=tx_out1 )
break;
403 ATOMIC_BLOCK( ATOMIC_RESTORESTATE ) {
404 UCSR1B|=( 1<<UDRIE1 );
410 tx_buff1[tx_in1] = *( uint8_t * )puffer++;
412 UCSR1B|=( 1<<UDRIE1 );
421 register uint8_t i=tx_in2;
423 if( i!=tx_out2 )
break;
424 ATOMIC_BLOCK( ATOMIC_RESTORESTATE ) {
425 UCSR2B|=( 1<<UDRIE2 );
431 tx_buff2[tx_in2] = *( uint8_t * )puffer++;
433 UCSR2B|=( 1<<UDRIE2 );
442 register uint8_t i=tx_in3;
444 if( i!=tx_out3 )
break;
445 ATOMIC_BLOCK( ATOMIC_RESTORESTATE ) {
446 UCSR3B|=( 1<<UDRIE3 );
452 tx_buff3[tx_in3] = *( uint8_t * )puffer++;
454 UCSR3B|=( 1<<UDRIE3 );
uint8_t eRTK_GetTid(void)
void eRTK_wefet(uint8_t timeout)
void eRTK_get_sema(uint8_t semaid)
void write(tUART port, void *puffer, uint8_t nbytes)
void eRTK_SetReady(uint8_t tid)
void deadbeef(tsys reason)
void eRTK_SetSuspended(uint8_t tid)
uint8_t read(tUART port, void *puffer, uint8_t nbytes, uint8_t timeout)